25LC160A-I/ST

Microchip Technology Inc. supports the Serial Peripheral Interface (SPI) compatible serial bus architecture with low-voltage serial Electrically Erasable PROMs (EEPROM) that range in density from 1 Kbits up to 1 Mbits. Byte-level and page-level functions are supported, but the higher density 512 Kbit and 1 Mbit devices also feature Sector and Chip erase functions typically associated with Flash-based products. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a Chip Select (CS) input. Communication to the device can be paused via the hold pin (HOLD). While the device is paused, transitions on its inputs will be ignored, with the exception of Chip Select, allowing the host to service higher priority interrupts. The entire series of SPI compatible devices are available in the standard 8-lead PDIP and SOIC packages, as well as the more advanced packages such as the 8-lead TSSOP, MSOP, 2x3 DFN, 5x6 DFN and 6-lead SOT-23. All packages are RoHS compliant with a Pb-free (Matte Tin) finish.

• Max Clock Speed
  • 10 MHz (1K-256K)
  • 20 MHz (512K-1M)
• Byte and Page-level Write Operations
• Low-power CMOS Technology
  • Typical Write current: 5 mA
  • Typical Read current: 5 mA @ 10 MHz 7 mA @ 20 MHz
  • Typical Standby current: 1 µA
• Write Cycle Time: 5 ms max. 6 ms max. (25XX1024)
• Self-timed Erase and Write Cycles
• Erase Functions (512K-1M)
  • Page Erase: 6 ms max.
  • Sector Erase: 15 ms max.
  • Chip Erase: 15 ms max.
• Built-in Write Protection
  • Power on/off data protection circuitry
  • Write enable latch
  • Write-protect pin
• Block/Sector Write Protection
  • Protect none, 1/4, 1/2 or all of array
• Sequential Read
• High Reliability
  • Data retention: > 200 years
  • ESD protection: > 4000V
  • Endurance > 1M Erase/Write Cycles
• Available in Standard 8-pin and 6-pin Pac