MX25U25635FZ4I-10G

The MX25U25635F is 256Mb bits Serial Flash memory, which is configured as 33,554,432 x 8 internally. When it is in two or four I/O mode, the structure becomes 134,217,728 bits x 2 or 67,108,864 bits x 4. MX25U25635F feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single I/O mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input.

When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# and RESET# pin become SIO0 pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output.

The MX25U25635F MXSMIO (Serial Multi I/O) provides sequential read operation on the whole chip.

After program/erase command is issued, auto program/erase algorithms which program/erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256 bytes) basis, or word basis for erase command is executed on 4K-byte sector, 32K-byte block, or 64K-byte block, or whole chip basis.

To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit.

When the device is not in operation and CS# is high, it is put in standby mode.

The MX25U25635F utilizes memory cell, which reliably stores memory contents even after 100,000 program and erase cycles.

• 256Mb serial flash memory
• Serial Peripheral Interface (SPI) compatible - Mode 0 and Mode 3
• Single Power Supply Operation
  • 1.65 to 2.0 volt for read, erase, and program operations
• 256Mb: 268,435,456 x 1 bit structure or 134,217,728 x 2 bits (two I/O mode) structure or 67,108,864 x 4 bits (four I/O mode) structure
• Protocol Support
  • Single I/O, Dual I/O and Quad I/O
• Latch-up protected to 100mA from -1V to Vcc +1V
• Low Vcc write inhibit is from 1.0V to 1.4V
• Fast read for SPI mode
  • Support clock frequency up to 108MHz for all protocols
  • Support clock frequency up to 133MHz for all protocols (for MX25U25635FZ4I-08G only)
  • Support Fast Read, 2READ, DREAD, 4READ, QREAD instructions.
  • Configurable dummy cycle number for fast read operation
• Quad Peripheral Interface (QPI) available
• Equal Sectors with 4K byte each, or Equal Blocks with 32K byte eac