PDP SEO Portlet

MX25R1635FZUIL0

NOR Flash Serial 1.8V/2.5V/3.3V 16Mbit 16M/8M/4M x 1Bit/2Bit/4Bit 8ns 8-Pin USON

Manufacturer:Macronix
Product Category: Memory, Flash Memory
Avnet Manufacturer Part #: MX25R1635FZUIL0
Secondary Manufacturer Part#: MX25R1635FZUIL0
  • Legend Information Icon RoHS 10 Compliant
  • Legend Information Icon Tariff Charges

The MX25R1635F is 16Mb bits serial Flash memory, which is configured as 2,097,152 x 8 internally. When it is in four I/ O mode, the structure becomes 4,194,304 bits x 4 or 8,388,608 bits x 2. MX25R1635F feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single I/O mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input.

When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# pin and Reset# pin become SIO0 pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output.

The MX25R1635F MXSMIO® (Serial Multi I/O) provides sequential read operation on whole chip.

After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256 bytes) basis, or word basis for erase command is executed on sector (4K-byte), or 32KB block (32K-byte), or block (64K-byte), or whole chip basis.

To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit.

Advanced security features enhance the protection and security functions.

The MX25R1635F utilizes memory cell, which reliably stores memory contents even after 100,000 program and erase cycles.

  • 16Mb serial flash memory
  • Serial Peripheral Interface (SPI) compatible - Mode 0 and Mode 3
  • 16,777,216 x 1 bit structure or 8,388,608 x 2 bits (two I/O mode) structure or 4,194,304 x 4 bits (four I/O mode) structure
  • Equal Sectors with 4K byte each, Equal Blocks with 32K byte each, or Equal Blocks with 64K byte each
    • Any Block can be erased individually
  • Single Power Supply Operation
    • 1.7 to 3.6 volt for read, erase, and program operations
  • Latch-up protected to 100mA from -1V to Vcc +1V
  • Low Vcc write inhibit is from 1.1V to 1.5V

Technical Attributes

Find Similar Parts

Description Value
8 ns
Sectored
Symmetrical
No
NOR
16 MB
No
Yes
Serial
Serial
60/Chip s
12 mA
2.4/Page ms
8 ns
16 Mbit
Surface Mount
8
1, 2, 4 Bit
16, 8, 4 MWords
-40 to 85 °C
85 °C
-40 °C
8USON
8
2 x 3 x 0.515 mm
15 mA
No
Industrial
No
USON
1.8, 2.5 V
1.8, 2.5, 3.3 V

ECCN / UNSPSC / COO

Description Value
Country of Origin: RECOVERY FEE
ECCN: 3A991.B.1.B.1
HTSN: 8542320071
Schedule B: 8542320040
In Stock :  0
Additional inventory
Factory Lead Time: 140 Weeks
Price for: Each
Quantity:
Min:12000  Mult:12000  
USD $:
12000+
$0.67891
24000+
$0.67548
48000+
$0.67206
96000+
$0.66863
192000+
$0.6652