MX25L6406EM2I-12GF/TR

The device feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input.

When it is in Dual Output read mode, the SI and SO pins become SIO0 and SIO1 pins for data output.

The device provides sequential read operation on whole chip.

After program/erase command is issued, auto program/erase algorithms which program/erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page basis, or word basis for erase command is executes on sector, or block, or whole chip basis.

To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit.

Advanced security features enhance the protection and security functions.

When the device is not in operation and CS# is high, it is put in standby mode.

The device utilizes memory cell, which reliably stores memory contents even after typical 100,000 program and erase cycles.

• Single Power Supply Operation
  • 2.7 to 3.6 volt for read, erase, and program operations
• Supports Serial Peripheral Interface - Mode 0 and Mode 3
• 67,108,864 x 1 bit structure or 33,554,432 x 2 bits (Dual Output mode) structure
• 2048 Equal Sectors with 4K byte each
  • Any Sector can be erased individually
• 128 Equal Blocks with 64K byte each
  • Any Block can be erased individually
• Program Capability
  • Byte base
  • Page base (256 bytes)
• Latch-up protected to 100mA from -1V to Vcc +1V