IS66WVE4M16EALL-70BLI-TR

The IS66WVE4M16EALL integrated memory device containing 64Mbit Pseudo Static Random Access Memory using a self-refresh DRAM array organized as 4M words by 16 bits. The device includes several power saving modes : Partial Array Refresh mode where data is retained in a portion of the array and Deep Power Down mode. Both these modes reduce standby current drain. The die has separate power rails, Vddq and Vssq for the I/O to be run from a separate Power Supply: from the device core. PSRAM products are high-speed, CMOS pseudo-static random access memory developed for low-power, portable applications. The 64Mb DRAM core device is organized as 4 Meg x 16 bits. These devices include the industry-standard, asynchronous memory interface found on other low-power SRAM or pseudo-SRAM (PSRAM) offerings. For seamless operation on an asynchronous memory bus, PSRAM products incorporated a transparent self-refresh mechanism. The hidden refresh requires no additional support from the system memory controller and has no significant impact on device read/write performance. A user-accessible configuration registers (CR) defines how the PSRAM device performs onchip refresh and whether page mode read accesses are permitted. This register is automatically loaded with a default setting during power-up and can be updated at anytime during normal operation. Special attention has been focused on current consumption during self-refresh. This product includes two system-accessible mechanisms to minimize refresh current. Setting sleep enable (ZZ#) to LOW enables one of two low-power modes: partial-array refresh (PAR) or deep power-down (DPD). PAR limits refresh to only that part of the DRAM array that contains essential data.

• Asynchronous and page mode interface
• Dual voltage rails for optional performance
  • Vdd 1.8V, Vddq 1.8V
• Page mode read access
  • Interpage Read access : 70ns
  • Interapage Read access : 20ns
• Low Power Consumption
  • Asynchronous Operation< 30 mA
  • Interapage Read< 18mA
  • Standby < 180 uA (max)
  • Deep power-down (DPD) < 3uA (Typ)
• Low Power Feature
  • Temperature Controlled Refresh
  • Partial Array Refresh
  • Deep power-down (DPD) mode
• Operating temperature Range
  • Industrial and Automotive, A1: -40°C to 85°C
• Package: 48-ball TFBGA, 48-pin TSOP-I