IS62C10248AL-55TLI
SRAM Chip Async Single 5V 8M-Bit 1M x 8 55ns 44-Pin TSOP-II
The IS62C10248 are high speed, 8M bit static RAMs organized as 1M words by 8 bits. It is fabricated high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high performance and low power consumption devices. When CS1 is HIGH (deselected) or when CS2 is low (deselected), the device assumes a standby mode at which the power dpation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS62C10248 are packaged in the JEDEC standard 44-Pin TSOP (TYPE II).
- High-speed access time: 45ns, 55ns
- CMOS low power operation
- 36 mW (typical) operating
- 12 µW (typical) CMOS standby
- TTL compatible interface levels
- Single power supply: 4.5V-5.5V Vdd
- Three state outputs
- Automotive temperature (-40°C to +125°C)
- Lead-free available
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| 20 Bit | ||
| 8 Mbit | ||
| Matte Tin | ||
| 260 | ||
| 25 mA | ||
| 55 ns | ||
| 8 Mbit | ||
| Surface Mount | ||
| MSL 3 - 168 hours | ||
| 44 | ||
| 8 Bit | ||
| 8 Bit | ||
| 1 | ||
| 1 MWords | ||
| -40 to 85 °C | ||
| 85 °C | ||
| -40 °C | ||
| 44TSOP-II | ||
| 44 | ||
| 18.52 x 10.29 x 1.05 mm | ||
| No | ||
| Industrial | ||
| TSOP-II | ||
| 5.5 V | ||
| 4.5 V | ||
| 5 V | ||
| Asynchronous | ||
| 5.0000 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | 3A991.B.2.A |
| HTSN: | 8542320041 |
| Schedule B: | 8542320040 |
Factory Lead Time: