IS61WV5128EDBLL-10TLI-TR
SRAM Chip Async Single 3.3V 4M-Bit 512K x 8 10ns 44-Pin TSOP-II T/R
The IS61WV5128EDBLL is a high-speed, 4,194,304-bit static RAMs organized as 524,288 words by 8 bits.It is fabricated using high-performance CMOS technology.This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CE\ is HIGH (deselected), the device assumes a standby mode at which the power dpation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE\ and OE\. The active LOW Write Enable (WE\) controls both writing and reading of the memory. The IS61WV5128EDBLL is packaged in the JEDEC standard 44-pinTSOP-II, 36-pin SOJ and 36-pin Mini BGA (6mm x 8mm).
- High-speed access time: 8, 10 ns
- Low Active Power: 85 mW (typical)
- Low Standby Power: 7 mW (typical) CMOS standby
- Single power supply
- Vdd 2.4V to 3.6V (10 ns)
- Vdd 3.3V ± 10% (8 ns)
- Fully static operation: no clocks or refresh required
- Three state outputs
- Commercial and Industrial temperature support
- Lead-free available
- Error Detection and Error Correction
Technical Attributes
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| Description | Value | |
|---|---|---|
| 19 Bit | ||
| SDR | ||
| 4 Mbit | ||
| Matte Tin | ||
| 260 °C | ||
| 25 mA | ||
| 10 ns | ||
| 4 Mbit | ||
| Surface Mount | ||
| MSL 3 - 168 hours | ||
| 44 | ||
| 8 Bit | ||
| 8 Bit | ||
| 1 | ||
| 512 kWords | ||
| -40 to 85 °C | ||
| 85 °C | ||
| -40 °C | ||
| 44TSOP-II | ||
| 44 | ||
| 18.41 x 10.16 x 1 mm | ||
| No | ||
| Industrial | ||
| TSOP-II | ||
| 3.6 V | ||
| 2.4 V | ||
| 3 V | ||
| Asynchronous | ||
| 3.3000 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | 3A991.B.2.A |
| HTSN: | 8542320041 |
| Schedule B: | 8542320040 |
Factory Lead Time: