IS61WV3216BLL-12TLI-TR
SRAM Chip Async Single 3.3V 512K-Bit 32K x 16 12ns 44-Pin TSOP-II T/R
The IS61WV3216BLL isahigh-speed,524,288-bit static RAM organized as 32,768 words by 16 bits. It is fabricated using high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 12ns (3.3V + 10%) and 15ns (2.5V-3.6V) with low power consumption. When CE\ is HIGH (deselected), the device assumes a standby mode at which the power dpation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE \ and OE\. The active LOW Write Enable (WE\) controls both writing and reading of the memory. A data byte allows Upper Byte (UB\) and Lower Byte (LB\) access. The IS61WV3216BLL is packaged in the JEDEC standard 44-pin TSOP-II, and 48-pin mini BGA (6mm x 8mm).
- High-speed access time: 12 ns: 3.3V + 10% 15 ns: 2.5V-3.6V
- CMOS low power operation: 50 mW (typical) operating 25 µW (typical) standby
- TTL compatible interface levels
- Fully static operation: no clocks or refresh required
- Three state outputs
- Data control for upper and lower bytes
- Commercial and Industrial Temperature Available
- Lead-free available
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| 15 Bit | ||
| SDR | ||
| 512 Kb | ||
| Matte Tin | ||
| 260 °C | ||
| 45 mA | ||
| 12 ns | ||
| 512 Kb | ||
| Surface Mount | ||
| MSL 3 - 168 hours | ||
| 44 | ||
| 16 Bit | ||
| 16 Bit | ||
| 1 | ||
| 32 kWords | ||
| -40 to 85 °C | ||
| 85 °C | ||
| -40 °C | ||
| 44TSOP-II | ||
| 44 | ||
| 18.41 x 10.16 x 1 mm | ||
| No | ||
| Industrial | ||
| Asynchronous SRAM | ||
| TSOP-II | ||
| 3.3 V | ||
| Asynchronous | ||
| 3.3000 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | 3A991.B.2.B |
| HTSN: | 8542320041 |
| Schedule B: | 8542320040 |