IS61QDPB42M36A2-500M3LI

The 72Mb IS61QDPB42M36 are synchronous, high performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. The following are registered internally on the rising edge of the K clock: Read address, Read enable, Write enable, Data-in for early writes. The following are registered on the rising edge of the K# clock: Write address, Byte writes, Data-in for second burst addresses. Byte writes can change with the corresponding data-in to enable or disable writes on a per-byte basis. An internal write buffer enables the data-ins to be registered half a cycle earlier than the write address. The first data-in burst is clocked at the same time as the write command signal, and the second burst is timed to the following rising edge of the K# clock. During the burst read operation, the data-outs from the first bursts are updated from output registers of the second rising edge of the K# clock (starting two and half cycles later after read command). The data-outs from the second bursts are updated with the third rising edge of the K clock. The K and K# clocks are used to time the data-outs. The device is operated with a single +1.8V power supply and is compatible with HSTL I/O interface.

• 2Mx36 configuration available
• On-chip Delay-Locked Loop (DLL) for wide data valid window
• Separate independent read and write ports with concurrent read and write operations
• Synchronous pipeline read with EARLY write operation
• Double Data Rate (DDR) interface for read and write input ports
• 2.5 Cycle read latency
• Fixed 2-bit burst for read and write operations
• Clock stop support
• Two input clocks (K and K#) for address and control registering at rising edges only
• Two echo clocks (CQ and CQ#) that are delivered simultaneously with data
• Data valid pin (QVLD)
• +1.8V core power supply and 1.5, 1.8V Vddq, used
• with 0.75, 0.9V Vref. HSTL input and output interface
• Registered addresses, write and read controls, byte writes, data in, and data outputs
• Full data coherency
• Boundary scan using limited set of JTAG 1149.1 functions
• Byte Write capability
• Fine bal