IS61QDP2B451236A-400M3L

The IS61QDP2B451236 are synchronous, high performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are self-time. The following are registered internally on the rising edge of the K clock: Read/write address, Read enable ,Write enable ,Byte writes for burst addresses 1 and 3 ,Data-in for burst addresses 1 and 3. The following are registered on the rising edge of the K# clock: Byte writes for burst addresses 2 and 4, Data-in for burst addresses 2 and 4. Byte writes can change with the corresponding data-in to enable or disable writes on a per-byte basis. An internal write buffer enables the data-ins to be registered one cycle after the write address. The first data-in burst is clocked one cycle later than the write command signal, and the second burst is timed to the following rising edge of the K# clock. Two full clock cycles are required to complete a write operation. During the burst read operation, the data-outs from the first and third bursts are updated from output registers of the third and fourth rising edges of the K clock (starting 2.0 cycles later after read command). The data-outs from the second and fourth bursts are updated with the third and fourth rising edges of the K# clock where the read command receives at the first rising edge of K. Two full clock cycles are required to complete a read operation. The device is operated with a single +1.8V power supply and is compatible with HSTL I/O interfaces.

• 512Kx36 configuration available
• On-chip Delay-Locked Loop (DLL) for wide datavalid window
• Separate independent read and write ports withconcurrent read and write operations
• Synchronous pipeline read with late write operation
• Double Data Rate (DDR) interface for read andwrite input ports
• 2.0 cycle read latency
• Fixed 4-bit burst for read and write operations
• Clock stop support
• Two input clocks (K and K#) for address and controlregistering at rising edges only
• Two echo clocks (CQ and CQ#) that are deliveredsimultaneously with data
• Data Valid Pin (QVLD)
• +1.8V core power supply and 1.5, 1.8V Vddq, usedwith 0.75, 0.9V Vref
• HSTL input and output interface
• Registered addresses, write and read controls, bytewrites, data in, and data outputs
• Full data coherency
• Boundary scan using limited set of JTAG 1149.1functions
• Byte write capability
• Fine ball grid a