IS61QDB42M36A-300M3L

The 72Mb IS61QDB42M36A and IS61QDB44M18A are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Read and write addresses are registered on alternating rising edges of the K clock. Reads and writes are performed in double data rate. The following are registered internally on the rising edge of the K clock: Read/write address, Read enable ,Write enable ,Byte writes for burst addresses 1 and 3 ,Data-in for burst addresses 1 and 3. The following are registered on the rising edge of the K# clock: Byte writes for burst addresses 2 and 4, Data-in for burst addresses 2 and 4. Byte writes can change with the corresponding data-in to enable or disable writes on a per-byte basis. An internal write buffer enables the data-ins to be registered one cycle after the write address. The first data-in burst is clocked one cycle later than the write command signal, and the second burst is timed to the following rising edge of the K# clock. Two full clock cycles are required to complete a write operation. During the burst read operation, the data-outs from the first and third bursts are updated from output registers of the second and third rising edges of the C# clock (starting 1.5 cycles later after read command). The data-outs from the second and fourth bursts are updated with the third and fourth rising edges of the C clock. The K and K# clocks are used to time the data-outs whenever the C and C# clocks are tied high. Two full clock cycles are required to complete a read operation. The device is operated with a single +1.8V power supply and is compatible with HSTL I/O interfaces.

• 2M x 36
• On-chip delay-locked loop (DLL) for wide datavalid window
• Separate read and write ports with concurrentread and write operations
• Synchronous pipeline read with early write operation
• Double data rate (DDR) interface for read andwrite input ports
• Fixed 2-bit burst for read and write operations
• Clock stop support
• Two input clocks (K and K) for address and controlregistering at rising edges only
• Two input clocks (C and C) for data output control
• Two echo Clocks (CQ and CQ) that are deliveredsimultaneously with data
• +1.8V core power supply and 1.5, 1.8V Vddq,used with 0.75, 0.9V Vref
• HSTL input and output levels
• Registered addresses, write and read controls,byte writes, data in, and data outputs
• Full data coherency
• Boundary scan using limited set of JTAG 1149.1functions
• Byte write capability
• Fine ball grid array (FBGA) package
  • 15mm x 17mm bod