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IS61NVP409618B-250B3L-TR

SRAM Chip Sync Dual 2.5V 72M-Bit 4M x 18 2.8ns 165-Pin TFBGA T/R

Manufacturer:ISSI
Product Category: Memory, SRAMs
Avnet Manufacturer Part #: IS61NVP409618B-250B3L-TR
Secondary Manufacturer Part#: IS61NVP409618B-250B3L-TR
  • Legend Information Icon RoHS 10 Compliant
  • Legend Information Icon Tariff Charges

The 72 Meg product family features high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications. They are organized as 4Mx18, fabricated with advanced CMOS technology. Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable, CKE\ is HIGH. In this state the internal device will hold their previous values. All Read, Write and Deselect cycles are initiated by the ADV input. When the ADV is HIGH the internal burst counter is incremented. New external addresses can be loaded when ADV is LOW. Write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when WE\ is LOW. Separate byte enables allow individual bytes to be written. A burst mode pin (MODE) defines the order of the burst sequence. When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the linear burst sequence is selected.

  • 100 percent bus utilization
  • No wait cycles between Read and Write
  • Internal self-timed write cycle
  • Individual Byte Write Control
  • Single R/W (Read/Write) control pin
  • Clock controlled, registered address, data and control
  • Interleaved or linear burst sequence control using MODE input
  • Three chip enables for simple depth expansion and address pipelining
  • Power Down mode
  • Common data inputs and data outputs
  • CKE pin to enable clock and suspend operation
  • JEDEC 100-pin TQFP, 165-ball PBGA and 119- ball PBGA packages
  • Power supply:
    • NVP: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%)
  • JTAG Boundary Scan for PBGA packages
  • Industrial temperature available
  • Lead-free available

Technical Attributes

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Description Value
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250 MHz
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260 °C
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450 mA
2.8 ns
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18 Bit
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2
4 MWords
0 to 70 °C
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165TFBGA
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13 x 15 x 0.79
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Commercial
2.5 V
2.5000 V

ECCN / UNSPSC / COO

Description Value
Country of Origin: RECOVERY FEE
ECCN: 3A991.B.2.A
HTSN: 8542320041
Schedule B: 8542320040
In Stock :  0
Additional inventory
Factory Lead Time: 84 Weeks
Price for: Each
Quantity:
Min:2000  Mult:2000  
USD $:
2000+
$123.97
4000+
$119.14
8000+
$114.31
16000+
$109.48
32000+
$107.4675