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IS61NLP102418B-200TQLI-TR

SRAM Chip Sync Dual 3.3V 18M-Bit 1M x 18 3ns 100-Pin LQFP T/R

Manufacturer:ISSI
Product Category: Memory, SRAMs
Avnet Manufacturer Part #: IS61NLP102418B-200TQLI-TR
Secondary Manufacturer Part#: IS61NLP102418B-200TQLI-TR
  • Legend Information Icon RoHS 10 Compliant
  • Legend Information Icon Tariff Charges

The 18Meg product family features high-speed, low power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications. They are organized as 1024K words by 18 bits, fabricated advanced CMOS technology. Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable, /CKE is HIGH. In this state the internal device will hold their previous values. All Read, Write and Deselect cycles are initiated by the ADV input. When the ADV is HIGH the internal burst counter is incremented. New external addresses can be loaded when ADV is LOW. Write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when /WE is LOW. Separate byte enables allow individual bytes to be written. A burst mode pin (MODE) defines the order of the burst sequence. When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the linear burst sequence is selected.

  • 100 percent bus utilization
  • No wait cycles between Read and Write
  • Internal self-timed write cycle
  • Individual Byte Write Control
  • Single R/W (Read/Write) control pin
  • Clock controlled, registered address, data and control
  • Interleaved or linear burst sequence control using MODE input
  • Three chip enables for simple depth expansion and address pipelining
  • Power Down mode
  • Common data inputs and data outputs
  • /CKE pin to enable clock and suspend operation
  • JEDEC 100-pin QFP, 165-ball BGA and 119- ball BGA packages
  • Power supply
    • Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%)
  • JTAG Boundary Scan for BGA packages
  • Commercial, Industrial and Automotive (x36) temperature support
  • Lead-free available.

Technical Attributes

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Description Value
20 Bit
Pipelined
200 MHz
SDR
18 Mbit
Matte Tin
260
200 MHz
3 ns
18 Mbit
Surface Mount
MSL 3 - 168 hours
100
18 Bit
18 Bit
2
1 MWords
-40 to 85 °C
85 °C
-40 °C
100LQFP
100
14 x 20 x 1.4
No
Industrial
Synchronous SRAM
LQFP
3.3 V
Synchronous
3.3000 V

ECCN / UNSPSC / COO

Description Value
Country of Origin: RECOVERY FEE
ECCN: 3A991.B.2.A
HTSN: 8542320041
Schedule B: 8542320040
In Stock :  0
Additional inventory
Factory Lead Time: 182 Weeks
Price for: Each
Quantity:
Min:800  Mult:800  
USD $:
800+
$15.93207
1600+
$15.8516
3200+
$15.77114
6400+
$15.69068
12800+
$15.61021