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IS61LPS102418B-200TQLI

SRAM Chip Sync Dual 3.3V 18M-Bit 1M x 18 100-Pin LQFP

Manufacturer:ISSI
Product Category: Memory, SRAMs
Avnet Manufacturer Part #: IS61LPS102418B-200TQLI
Secondary Manufacturer Part#: IS61LPS102418B-200TQLI
  • Legend Information Icon RoHS 10 Compliant
  • Legend Information Icon Tariff Charges

The 18Mb product family features high-speed, low power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications. The IS61LPS102418B are organized as 1,048,576 words by 18bits. Fabricated with advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. The byte write operation is performed by using the byte write enable (/BWE) input combined with one or more individual byte write signals (/BWx). In addition, Global Write (/GW) is available for writing all bytes at one time, regardless of the byte write control. Bursts can be initiated with either /ADSP(Address Status Processor) or /ADSC\ (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the /ADV\ (burst address advance) input pin. Bursts can be initiated with either /ADSP(Address Status Processor) or /ADSC\ (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the /ADV\ (burst address advance) input pin.

  • Internal self-timed write cycle
  • Individual Byte Write Control and Global Write
  • Clock controlled, registered address, data and
  • control
  • Burst sequence control using MODE input
  • Three chip enable option for simple depth expansion and address pipelining
  • Common data inputs and data outputs
  • Auto Power-down during deselect
  • Single cycle deselect
  • Snooze MODE for reduced-power standby
  • JEDEC 100-pin QFP, 165-ball BGA and 119-ball BGA packages
  • Power supply: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%)
  • JTAG Boundary Scan for BGA packages
  • Commercial, Industrial and Automotive temperature support
  • Lead-free available

Technical Attributes

Find Similar Parts

Description Value
20 Bit
Pipelined
200 MHz
SDR
18 Mbit
260
200 MHz
18 Mbit
Surface Mount
100
18 Bit
18 Bit
2
1 MWords
-40 to 85 °C
85 °C
-40 °C
100LQFP
100
14 x 20 x 1.4
No
Industrial
LQFP
3.465 V
3.135 V
3.3 V
Synchronous
3.3000 V

ECCN / UNSPSC / COO

Description Value
Country of Origin: RECOVERY FEE
ECCN: 3A991.B.2.A
HTSN: 8542320041
Schedule B: 8542320040
In Stock :  0
Additional inventory
Factory Lead Time: 84 Weeks
Price for: Each
Quantity:
Min:72  Mult:72  
USD $:
72+
$13.57143
144+
$12.83784
288+
$12.65964
576+
$12.59505
1152+
$11.91645