IS61C25616AS-25TLI-TR
SRAM Chip Async Single 5V 4M-Bit 256K x 16 25ns 44-Pin TSOP-II T/R
The IS61C25616AS are high-speed, 4,194,304-bit static RAMs organized as 262,144 words by 16 bits. They are fabricated using high performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 12 ns with low power consumption. When CE is HIGH (deselected), the device assumes a standby mode at which the power dpation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS61C25616AS are packaged in the JEDEC standard 44-pin 400-mil SOJ and 44-pin TSOP (Type II).
- Low Power
- High-speed access time: 25 ns
- Low Active Power: 75 mW (typical)
- Low Standby Power: 1 mW (typical) CMOS standby
- TTL compatible interface levels
- Single 5V ± 10% power supply
- Fully static operation: no clock or refresh required
- Available in 44-pin SOJ package and 44-pin TSOP (Type II)
- Commercial and Industrial temperature ranges available
- Lead-free available.
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| 18 Bit | ||
| 400 MHz | ||
| 4 Mbit | ||
| Matte Tin | ||
| 260 | ||
| 15 mA | ||
| 25 ns | ||
| 4 Mbit | ||
| Surface Mount | ||
| MSL 3 - 168 hours | ||
| 44 | ||
| 16 Bit | ||
| 16 Bit | ||
| 1 | ||
| 256 kWords | ||
| -40 to 85 °C | ||
| 85 °C | ||
| -40 °C | ||
| 44TSOP-II | ||
| 44 | ||
| 18.52 x 10.29 x 1.05 mm | ||
| No | ||
| Industrial | ||
| TSOP-II | ||
| 5.5 V | ||
| 4.5 V | ||
| 5 V | ||
| Asynchronous | ||
| 5.0000 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | 3A991.B.2.A |
| HTSN: | 8542320041 |
| Schedule B: | 8542320040 |