IS46DR16640C-3DBLA2
DRAM, DDR2, 1 Gbit, 64M x 16bit, 333 MHz, 84 Pins, TWBGA
IS46DR16640C-3DBLA2 is a 1Gb DDR2 SDRAM in an 84 pin TWBGA package. It uses a double-data-rate architecture to achieve high-speed operation. The double-data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls.
- 64Mx16bit memory configuration, 333MHz frequency
- Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V
- JEDEC standard 1.8V I/O (SSTL-18-compatible)
- Differential data strobe
- 4-bit prefetch architecture
- On chip DLL to align DQ and DQS transitions with CK
- 8 internal banks for concurrent operation
- Programmable CAS latency (CL) 3, 4, 5, 6 and 7 supported
- WRITE latency = READ latency - 1 tCK, programmable burst lengths: 4 or 8, on-die termination (ODT)
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| 333 MHz | ||
| DDR2 | ||
| TWBGA | ||
| Surface Mount | ||
| 64M x 16bit | ||
| 1 Gbit | ||
| MSL 3 - 168 hours | ||
| 84 | ||
| 105 °C | ||
| -40 °C | ||
| IS46DR Series | ||
| 1.8 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | EAR99 |
| HTSN: | 8542320032 |
| Schedule B: | 8542320015 |
Ships
in 1 bus. day