IS45S16100H-7TLA2

The 16Mb Synchronous DRAM IS42/4516100H is organized as a 524,288-word x 16-bit x 2-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.

• Clock frequency: 200, 166, 143 MHz
• Fully synchronous; all signals referenced to a positive Clock edge
• Two banks can be operated simultaneously and independently
• Dual internal bank controlled by A11 (bank select)
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length
  • (1, 2, 4, 8, full page)
• Programmable burst sequence: Sequential/Interleave
• 2048 refresh cycles every 32ms (Com, Ind, A1 grade) or 16ms (A2 grade)
• Random column address every Clock cycle
• Programmable CAS latency (2, 3 Clocks)
• Burst read/write and burst read/single write operations capability
• Burst termination by burst stop and precharge command
• Byte controlled by LDQM and UDQM
• Packages: 400-mil 50-pin TSOP-II and 60-ball TF-BGA
• Temperature Grades: Automotive A1 (-40°C to +85°C) Automotive A2 (-40°C to +105°C)