IS43TR16128CL-125KBL-TR
DRAM Chip DDR3L SDRAM 2Gbit 128M X 16 1.35V 96-Pin TWBGA T/R
- Standard Voltage: VDD and VDDQ: 1.5V ± 0.075V
- Low Voltage (L): VDD and VDDQ: 1.35V + 0.1V, -0.067V
- Backward compatible to 1.5V
- High speed data transfer rates with system frequency up to 1066 MHz
- 8 internal banks for concurrent operation
- 8n-Bit pre-fetch architecture
- Programmable CAS Latency
- Programmable Additive Latency: 0, CL-1,CL-2
- Programmable CAS WRITE latency (CWL) based on tCK
- Programmable Burst Length: 4 and 8
- Programmable Burst Sequence: Sequential or Interleave
- BL switch on the fly
- Auto Self Refresh(ASR)
- Self Refresh Temperature(SRT)
- Refresh Interval:
- 7.8 us (8192 cycles/64 ms) Tc: -40°C to 85°C
- 3.9 us (8192 cycles/32 ms) Tc: 85°C to 105°C
- Partial Array Self Refresh
- Asynchronous RESET pin
- TDQS (Termination Data Strobe) supported (x8 only)
- OCD (Off-Chip Driver Impedance Adjustment)
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| 14 Bit | ||
| 800 MHz | ||
| 16 Bit | ||
| 2 Gbit | ||
| DDR3L SDRAM | ||
| Tin-Silver-Copper | ||
| 260 °C | ||
| 800 MHz | ||
| 138 mA | ||
| 20 ns | ||
| 2 Gbit | ||
| Surface Mount | ||
| MSL 3 - 168 hours | ||
| 96 | ||
| 8 | ||
| 16 Bit | ||
| 16 Bit | ||
| 2.5, 1 V | ||
| 0 to 95 °C | ||
| 95 °C | ||
| 0 °C | ||
| 128M x 16 | ||
| 96TWBGA | ||
| 96 | ||
| 9 x 13 x 0.8 mm | ||
| Commercial | ||
| TWBGA | ||
| 1.35 V | ||
| DDR3L SDRAM |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | EAR99 |
| HTSN: | 8542320036 |
| Schedule B: | 8542320023 |
Factory Lead Time: