IS43R86400D-5BLI-TR

The 512-Mbit DDR SDRAM achieves high speed data transfer using pipeline architecture and two data word accesses per clock cycle. The 536,870,912-bit memory array is internally organized as four banks of 128Mb to allow concurrent operations. The pipeline allows Read and Write burst accesses to be virtually continuous, with the option to concatenate or truncate the bursts. The programmable features of burst length, burst sequence and CAS latency enable further advantages. The device is available in 8-bit, 16-bit and 32-bit data word size Input data is registered on the I/O pins on both edges of Data Strobe signal(s), while output data is referenced to both edges of Data Strobe and both edges of CLK. Commands are registered on the positive edges of CLK. An Auto Refresh mode is provided, along with a Self Refresh mode. All I/Os are SSTL_2 compatible.

• Vdd and Vddq: 2.5V ± 0.2V (-6)
• Vdd and Vddq: 2.6V ± 0.1V (-5)
• SSTL_2 compatible I/O
• Double-data rate architecture; two data transfers per clock cycle
• Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver
• DQS is edge-aligned with data for READs and centre-aligned with data for WRITEs
• Differential clock inputs (CK and CK)
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
• Four internal banks for concurrent operation
• Data Mask for write data. DM masks write data at both rising and falling edges of data strobe
• Burst Length: 2, 4 and 8
• Burst Type: Sequential and Interleave mode
• Programmable CAS latency: 2, 2.5 and 3
• Auto Refresh and Self Refresh Modes
• Auto Precharge
• TRAS Lockout Supported (tRAP = tRCD