IS43R16160F-5TL-TR

ISSI’s 256-Mbit DDR SDRAM achieves high speed datatransfer using pipeline architecture and two data wordaccesses per clock cycle. The 268,435,456-bit memoryarray is internally organized as four banks of 64Mb toallow concurrent operations. The pipeline allows Readand Write burst accesses to be virtually continuous, withthe option to concatenate or truncate the bursts. Theprogrammable features of burst length, burst sequenceand CAS latency enable further advantages. The deviceis available in 8-bit, 16-bit and 32-bit data word sizeInput data is registered on the I/O pins on both edgesof Data Strobe signal(s), while output data is referencedto both edges of Data Strobe and both edges of CLK.Commands are registered on the positive edges of CLK.

• VDD and VDDQ: 2.5V ± 0.2V
• SSTL_2 compatible I/O
• Double-data rate architecture; two data transfers per clock cycle
• Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver
• DQS is edge-aligned with data for READs and centre-aligned with data for WRITEs
• Differential clock inputs (CK and CK)
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
• Four internal banks for concurrent operation
• Data Mask for write data. DM masks write data at both rising and falling edges of data strobe
• Burst Length: 2, 4 and 8
• Burst Type: Sequential and Interleave mode
• Programmable CAS latency: 2, 2.5 and 3
• Auto Refresh and Self Refresh Modes
• Auto Precharge
• TRAS Lockout supported (tRAP = tRCD)