IS43LR32160C-6BLI

The IS43LR32160C-6BLI is a 536870912-bit CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 4194304 words x 32-bit. This product uses a double-data-rate architecture to achieve high-speed operation. The data input/output signals are transmitted on a 32-bit bus. The double data rate architecture is essentially a 2N pre-fetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 2n-bit pre-fetched to achieve very high bandwidth. All input and output voltage levels are compatible with LVCMOS.

• JEDEC standard 1.8V power supply
• 4-Internal banks for concurrent operation
• MRS cycle with address key programs
• Fully differential clock inputs
• All inputs except data & DM are sampled at the rising edge of the system clock
• Data I/O transaction on both edges of data strobe
• Bidirectional data strobe per byte of data
• DM for write masking only
• Edge aligned data and data strobe output
• Center aligned data and data strobe input