IS43LR16320C-6BLI

The IS43LR16320C is 536,870,912 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 8,388,608 words x 16 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The Data Input/ Output signals are transmitted on a 16-bit bus. The double data rate architecture is essentially a 2N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 2n-bits prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with LVCMOS.

• JEDEC standard 1.8V power supply
• Vdd = 1.8V, Vddq = 1.8V
• Four internal banks for concurrent operation
• MRS cycle with address key programs
  • CAS latency 2, 3 (Clock)
  • Burst length (2, 4, 8, 16)
  • Burst type (sequential and interleave)
• Fully differential Clock inputs (CK, /CK)
• All inputs except data and DM are sampled at the rising edge of the system Clock
• Data I/O transaction on both edges of data strobe
• Bidirectional data strobe per byte of data (DQS)
• DM for write masking only
• Edge aligned data and data strobe output
• Center aligned data and data strobe input
• 64ms refresh period (8K cycle)
• Auto and self refresh
• Concurrent Auto Precharge
• Maximum Clock frequency up to 200MHZ
• Maximum data rate up to 400Mbps/pin
• Power Saving support
  • PASR (Partial Array Self Refresh)
  • Auto TCSR (Temperature Compensated Self Refresh)<