IS43LR16160H-6BLI

IS43LR16160H-6BLI is a CMOS mobile double data rate synchronous DRAM organized as 4 banks of 4,194,304 words x 16 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The Data Input/ Output signals are transmitted on a 16-bit bus. The double data rate architecture is essentially a 2N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 2n-bits prefetched to achieve very high bandwidth.

• 16Mx16bit memory configuration, 256Mbit memory density, 166MHz frequency
• Four internal banks for concurrent operation
• MRS cycle with address key programs
• Fully differential clock inputs (CK, /CK)
• All inputs except data & DM are sampled at the rising edge of the system clock
• Data I/O transaction on both edges of data strobe
• Bidirectional data strobe per byte of data (DQS)
• DM for write masking, edge aligned data & data strobe o/p, centre aligned data & data strobe i/p
• Power saving support, status register read (SRR), LVCMOS compatible inputs/outputs
• Operating temperature range from -40 to 85°C