IS43DR81280C-3DBLI
DRAM Chip DDR2 SDRAM 1G-Bit 128Mx8 1.8V 60-Pin TWBGA
The IS43DR81280C 1Gb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls.
- Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V
- JEDEC standard 1.8V I/O (SSTL_18-compatible)
- Double data rate interface: two data transfers per clock cycle
- Differential data strobe (DQS, DQS)
- 4-bit prefetch architecture
- On chip DLL to align DQ and DQS transitions with CK
- 8 internal banks for concurrent operation
- Programmable CAS latency (CL) 3, 4, 5, 6 and 7 supported
- Posted CAS and programmable additive latency (AL) 0, 1, 2, 3, 4, 5 and 6 supported
- WRITE latency = READ latency - 1 tCK
- Programmable burst lengths: 4 or 8
- Adjustable data-output drive strength, full and reduced strength options
- On-die termination (ODT)
- Configuration(s): 128Mx8 (16Mx8x8 banks): IS43DR81280C
- Package: x8: 60-ball BGA (8mm x 10.5mm)
- Timing – Cycle time
- 2.5ns @CL=5 DDR2-800D
- 2.5ns @CL=6 DDR2-800E
- 3.0ns @CL=5 DDR2-667D
- 3.75ns @CL=4 DDR2-533C
- 5ns @CL=3 DDR
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| 14 Bit | ||
| 333 MHz | ||
| 8 Bit | ||
| 1 Gbit | ||
| DDR2 SDRAM | ||
| Tin-Silver-Copper | ||
| 260 °C | ||
| 333 MHz | ||
| 105 mA | ||
| 0.45 ns | ||
| 1 Gbit | ||
| Surface Mount | ||
| MSL 3 - 168 hours | ||
| 60 | ||
| 8 | ||
| 8 Bit | ||
| 8 Bit | ||
| 1.8000 V | ||
| -40 to 85 °C | ||
| 85 °C | ||
| -40 °C | ||
| 128M x 8 | ||
| 60TWBGA | ||
| 60 | ||
| 8 x 10.5 x 0.8(Max) | ||
| Industrial | ||
| 1.8 V | ||
| DDR2 SDRAM |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | EAR99 |
| HTSN: | 8542320032 |
| Schedule B: | 8542320015 |
Factory Lead Time: