IS43DR81280C-25DBL

The IS43DR81280C 1Gb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls.

• Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V
• JEDEC standard 1.8V I/O (SSTL_18-compatible)
• Double data rate interface: two data transfers per clock cycle
• Differential data strobe (DQS, DQS)
• 4-bit prefetch architecture
• On chip DLL to align DQ and DQS transitions with CK
• 8 internal banks for concurrent operation
• Programmable CAS latency (CL) 3, 4, 5, 6 and 7 supported
• Posted CAS and programmable additive latency (AL) 0, 1, 2, 3, 4, 5 and 6 supported
• WRITE latency = READ latency - 1 tCK
• Programmable burst lengths: 4 or 8
• Adjustable data-output drive strength, full and reduced strength options
• On-die termination (ODT)
• Configuration(s): 128Mx8 (16Mx8x8 banks): IS43DR81280C
• Package: x8: 60-ball BGA (8mm x 10.5mm)
• Timing – Cycle time
  • 2.5ns @CL=5 DDR2-800D
  • 2.5ns @CL=6 DDR2-800E
  • 3.0ns @CL=5 DDR2-667D
  • 3.75ns @CL=4 DDR2-533C
  • 5ns @CL=3 DDR