IS43DR81280B-3DBL-TR
DRAM Chip DDR2 SDRAM 1G-Bit 128M X 8 1.8V 60-Pin TWBGA T/R
- Clock frequency up to 400MHz
- 8 internal banks for concurrent operation
- 4-bit prefetch architecture
- Programmable CAS Latency: 3, 4, 5, 6 and 7
- Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6
- Write Latency = Read Latency-1
- Programmable Burst Sequence: Sequential or Interleave
- Programmable Burst Length: 4 and 8
- Automatic and Controlled Precharge Command
- Power Down Mode
- Auto Refresh and Self Refresh
- Refresh Interval: 7.8 µs (8192 cycles/64 ms)
- ODT (On-Die Termination)
- Weak Strength Data-Output Driver Option
- Bidirectional differential Data Strobe (Single ended data-strobe is an optional feature)
- On-Chip DLL aligns DQ and DQs transitions with CK transitions
- DQS# can be disabled for single-ended data strobe
- Read Data Strobe supported (x8 only)
- Differential clock inputs CK and CK#
- VDD and VDDQ = 1.8V ± 0.1V
- PASR (Partial
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| 14 Bit | ||
| 333 MHz | ||
| 8 Bit | ||
| 1 Gbit | ||
| DDR2 SDRAM | ||
| Tin-Silver-Copper | ||
| 260 °C | ||
| 333 MHz | ||
| 105 mA | ||
| 8 ns | ||
| 128M x 8bit | ||
| 1 Gbit | ||
| Surface Mount | ||
| MSL 3 - 168 hours | ||
| 60 | ||
| 8 | ||
| 8 Bit | ||
| 8 Bit | ||
| 1.8000 V | ||
| 0 to 70 °C | ||
| 70 °C | ||
| 0 °C | ||
| 128M x 8 | ||
| 60TWBGA | ||
| 60 | ||
| 8 x 10.5 x 0.8 mm | ||
| Commercial | ||
| TWBGA | ||
| DDR2 SDRAM |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | EAR99 |
| HTSN: | 8542320032 |
| Schedule B: | 8542320015 |
Lead Time Unavailable