IS43DR16128C-25DBL-TR
DRAM Chip DDR2 SDRAM 2G-Bit 128Mx16 1.8V 84-Pin TWBGA T/R
The IS43DR16128C 2Gb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls.
- Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V
- JEDEC standard 1.8V I/O (SSTL_18-compatible)
- Double data rate interface: two data transfers per clock cycle
- Differential data strobe (DQS, DQS)
- 4-bit prefetch architecture
- On chip DLL to align DQ and DQS transitions with CK
- 8 internal banks for concurrent operation
- Programmable CAS latency (CL) 3, 4, 5, 6, and 7 supported
- Posted CAS and programmable additive latency (AL) 0, 1, 2, 3, 4, 5, and 6 supported
- WRITE latency = READ latency - 1 tCK
- Programmable burst lengths: 4 or 8
- Adjustable data-output drive strength, full and reduced strength options
- On-die termination (ODT)
- Configuration(s): 128Mx16 (16Mx16x8 banks) IS43DR16128C
- Package: 84-ball WBGA (8mm x 12.5mm)
- Temperature Range: Commercial (0°C = Tc = 85°C) Industrial (-40°C = Tc = 95°C; -40°C = Ta = 85°C)
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| 14 Bit | ||
| 400 MHz | ||
| 16 Bit | ||
| 2 Gbit | ||
| DDR2 SDRAM | ||
| Tin-Silver-Copper | ||
| 260 °C | ||
| 400 MHz | ||
| 108 mA | ||
| 0.4 ns | ||
| 2 Gbit | ||
| Surface Mount | ||
| MSL 3 - 168 hours | ||
| 84 | ||
| 8 | ||
| 16 Bit | ||
| 16 Bit | ||
| 1.8000 V | ||
| 0 to 85 °C | ||
| 85 °C | ||
| 0 °C | ||
| 128M x 16 | ||
| 84TWBGA | ||
| T/R | ||
| 84 | ||
| 8 x 12.5 x 0.8(Max) | ||
| Commercial | ||
| 1.8 V | ||
| DDR2 SDRAM |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | EAR99 |
| HTSN: | 8542320036 |
| Schedule B: | 8542320015 |
Factory Lead Time: