IS42SM16800H-75BLI-TR
DRAM Chip Mobile SDRAM 128M-Bit 8Mx16 3.3V 54-Pin TFBGA T/R
The IS42SM16800H are mobile 134,217,728 bits CMOS Synchronous DRAM organized as 4 banks of 2,097,152 words x 16 bits. These products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve high bandwidth. All input and output voltage levels are compatible with LVCMOS.
- JEDEC standard 3.3V power supply
- Auto refresh and self refresh
- All pins are compatible with LVCMOS interface
- 4K refresh cycle / 64ms
- Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full Page for Sequential Burst
- 4 or 8 for Interleave Burst
- Programmable CAS Latency : 2,3 clocks
- All inputs and outputs referenced to the positive edge of the system clock
- Data mask function by DQM
- Internal dual banks operation
- Burst Read Single Write operation
- Special Function Support
- PASR(Partial Array Self Refresh)
- Auto TCSR(Temperature Compensated Self Refresh)
- Programmable Driver Strength Control
- Full Strength or 1/2, 1/4, of Full Strength
- Deep Power Down Mode
- Automatic precharge, includes CONCURRENT Auto Precharge Mode and controlled Precharge
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| 12 Bit | ||
| 133 MHz | ||
| 16 Bit | ||
| 128 Mbit | ||
| Tin-Silver-Copper | ||
| 260 °C | ||
| 133 MHz | ||
| 45 mA | ||
| 8|6 ns | ||
| 128 Mbit | ||
| Surface Mount | ||
| MSL 3 - 168 hours | ||
| 54 | ||
| 4 | ||
| 16 Bit | ||
| 16 Bit | ||
| 3.3000 V | ||
| -40 to 85 °C | ||
| 85 °C | ||
| -40 °C | ||
| 8M x 16 | ||
| 54TFBGA | ||
| T/R | ||
| 54 | ||
| 8 x 8 x 0.8(Max) | ||
| Industrial | ||
| 3.3 V | ||
| Mobile SDRAM |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | EAR99 |
| HTSN: | 8542320002 |
| Schedule B: | 8542320015 |
Factory Lead Time: