IS42RM32400H-6BLI
DRAM Chip Mobile SDRAM 128M-Bit 4Mx32 2.5V 90-Pin TF-BGA
These IS42RM32400H are mobile 134,217,728 bits CMOS Synchronous DRAM organized as 4 banks of 1,048,576 words x 32 bits. These products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve high bandwidth. All input and output voltage levels are compatible with LVCMOS.
- JEDEC standard 2.5V power supply
- Auto refresh and self refresh
- All pins are compatible with LVCMOS interface
- 4K refresh cycle / 64ms
- Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full Page for Sequential Burst
- 4 or 8 for Interleave Burst
- Programmable CAS Latency : 2,3 clocks
- All inputs and outputs referenced to the positive edge of thesystem clock
- Data mask function by DQM
- Internal 4 banks operation
- Burst Read Single Write operation
- Special Function Support
- PASR(Partial Array Self Refresh)
- Auto TCSR(Temperature Compensated Self Refresh)
- Programmable Driver Strength Control
- Full Strength or 1/2, 1/4 of Full Strength
- Deep Power Down Mode
- Automatic precharge, includes CONCURRENT Auto PrechargeMode and controlled Precharge
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| 12 Bit | ||
| 166 MHz | ||
| 32 Bit | ||
| 128 Mbit | ||
| Mobile SDRAM | ||
| Tin-Silver-Copper | ||
| 260 °C | ||
| 166 MHz | ||
| 55 mA | ||
| 8|5.5 ns | ||
| 4M x 32bit | ||
| 128 Mbit | ||
| Surface Mount | ||
| MSL 3 - 168 hours | ||
| 90 | ||
| 4 | ||
| 32 Bit | ||
| 32 Bit | ||
| 2.5000 V | ||
| -40 to 85 °C | ||
| 85 °C | ||
| -40 °C | ||
| 4M x 32 | ||
| 90TF-BGA | ||
| 90 | ||
| 8 x 13 x 0.8(Max) | ||
| Industrial | ||
| Mobile SDRAM |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | EAR99 |
| HTSN: | 8542320002 |
| Schedule B: | 8542320015 |
Factory Lead Time: