IS25LP128-JLLE

The IS25LP128 Serial Flash memory offers a storage solution with the flexibility and performance in a simplified pin count package. ISSI’s “Industry Standard Serial Interface” Flash are for systems that have limited space, pins, and power. The IS25LP128 are accessed through a 4-wire SPI Interface consisting of a Serial Data Input (Sl), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins, which also serve as multi-I/O. The device supports the standard Serial Peripheral Interface (SPI), Dual/Quad output (SPI), and Dual/Quad I/O (SPI). Clock frequencies of up to 133MHz allow for equivalent clock rates of up to 532MHz (133MHz x 4) allowing more than 66Mbytes/s of throughput. The IS25xP series of Flash adds support for DTR (Double Transfer Rate) commands that transfer addresses and read data on both edges of the clock. These transfer rates can outperform 16-bit Parallel Flash memories allowing for efficient memory access for a XIP (execute in place) operation. The memory array is organized into programmable pages of 256-bytes each. The IS25LP128 supports page program mode where 1 to 256 bytes of data can be programmed into the memory with one command. QPI (Quad Peripheral Interface) supports 2-cycle instruction further reducing instruction times. Pages can be erased in groups of 4K-byte sectors, 32K-byte blocks, 64K-byte blocks, and/or the entire chip. The uniform sectors and blocks allow greater flexibility for a variety of applications requiring solid data retention.

• Industry Standard Serial Interface
  • IS25LP128:128M-bit/16M-byte
  • 256 bytes per Programmable Page
  • Supports standard SPI, Fast, Dual, Dual I/O, QPI, SPI DTR, Dual SPI DTR I/O, and QPI DTR
  • Supports Serial Flash Discoverable Parameters (SFDP)
• High Performance Serial Flash (SPI)
  • 50MHz Normal and 133Mhz Fast Read
  • 532 MHz equivalent QPI
  • DTR (Dual Transfer Rate) up to 66MHz
  • Selectable dummy cycles
  • Configurable drive strength
  • Supports SPI Modes 0 and 3
  • More than 100,000 erase/program cycles
  • More than 20-year data retention
• Flexible & Efficient Memory Architecture
  • Chip Erase:128Mbit with Uniform: Sector/Block Erase (4K/32K/64K-Byte)
  • Program 1 to 256 bytes per page
  • Program/Erase Suspend & Resume
• Efficient Read and Program modes
  • Low Instruction Overhead Operations
  • Continuous Read 8/16/32/64-Byte burst