S29PL127J60TFI130

The PL127J is a 128 Mbit, 3.0 volt-only Page Mode and Simultaneous Read/Write Flash memory device organized as 8 Mwords. The devices are offered in the following packages: – 11 mm x 8 mm, 80-ball Fine-pitch BGA standalone (PL127J) – 8 mm x 11.6 mm, 64-ball Fine-pitch BGA multi-chip compatible (PL127J) – 20 mm x 14 mm, 56-pin TSOP (PL127J) The word-wide data (x16) appears on DQ15-DQ0. This device can be programmed in-system or in standard EPROM programmers. A 12.0 V VPP is not required for write or erase operations. The device offers fast page access times of 20 to 30 ns, with corresponding random access times of 55 to 70 ns, respectively, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.

• Architectural Advantages
• 128 Mbit Page Mode devices
  • Page size of 8 words: Fast page read access from random locations within the page
• Single power supply operation
  • Full Voltage range: 2.7 to 3.6 volt read, erase, and program operations for battery-powered applications
• Simultaneous Read/Write Operation
  • Data can be continuously read from one bank while executing erase/ program functions in another bank
  • Zero latency switching from write to read operations
• FlexBank Architecture (PL127J)
  • 4 separate banks, with up to two simultaneous operations per device
  • Bank A: PL127J -16 Mbit (4 Kw x 8 and 32 Kw x 31)
  • Bank B: PL127J - 48 Mbit (32 Kw x 96)
  • Bank C: PL127J - 48 Mbit (32 Kw x 96)
  • Bank D: PL127J -16 Mbit (4 Kw x 8 and 32 Kw x 31)
• Enhanced VersatileI/O (VIO) Control
  • Output voltage generated and input voltages tolerated on all con