S25FS256SDSNFI000

S25FS256SDSNFI000 is a FS-S flash non-volatile memory using MIRRORBIT™ technology - that stores two data bits in each memory array transistor, eclipse architecture - that dramatically improves program and erase performance, 65-nm process lithography. This multiple width interface is called SPI multi-I/O or MIO. In addition, the FL-S family adds support for DDR read commands for SIO, DIO, and QIO that transfer address and read data on both edges of the clock. The eclipse architecture features a page programming buffer that allows up to 128 words (256bytes) or 256 words (512bytes) to be programmed in one operation, resulting in faster effective programming and erase than prior generation SPI program or erase algorithms.

• 256Mbit density, 65nm MIRRORBIT™ Process Technology, 80MHz DDR speed
• 8-contact WSON package type
• Industrial temperature range from –40°C to + 85°C
• SPI clock polarity and phase modes 0 and 3
• Commands, Normal, fast, dual, quad, fast DDR, dual DDR, quad DDR
• Modes, burst wrap, continuous (XIP), QPI, program suspend and resume
• Security features, one-time program (OTP) array of 1024bytes
• Erase suspend and resume, erase status evaluation
• 100000 program-erase cycles (minimum), 20 year data retention (minimum)