CY8CKIT-042
Development Kit For PSoC 4200 Device Family
- RoHS 10 Compliant
- Tariff Charges
PSoC 4 is a scalable and reconfigurable platform architecture for a family of mixed-signal programmable embedded system controllers with an ARM Cortex-M0 CPU. It combines programmable and re-configurable analog and digital blocks with flexible automatic routing. The PSoC 4200 product family, based on this platform, is a combination of a microcontroller with digital programmable logic, high-performance analog-to-digital conversion, opamps with Comparator mode, and standard communication and timing peripherals. The PSoC 4200 products will be fully upward compatible with members of the PSoC 4 platform for new applications and design needs. The programmable analog and digital sub-systems allow flexibility and in-field tuning of the design.
- 32-bit MCU Sub-system
- 48 MHz ARM Cortex-M0 CPU with single cycle multiply
- Up to 32 kB of flash with Read Accelerator
- Up to 4 kB of SRAM
- Programmable Analog
- Two opamps with reconfigurable high-drive external and high-bandwidth internal drive and Comparator modes and ADC input buffering capability
- 12-bit 1 Msps SAR ADC with differential and single-ended modes and Channel Sequencer with signal averaging
- Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin
- Two low-power comparators that operate in Deep Sleep
- Programmable Digital
- Four programmable logic blocks, each with 8 Macrocells and data path (called universal digital blocks, UDBs)
- Cypress provided peripheral component library, user-defined state machines, and Verilog input
- Low Power 1.71 to 5.5 V operation
- 20 nA Stop Mode with GPIO pin wakeup
- Hiberna
Technical Attributes
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ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | 3A991.A.2 |
| HTSN: | 8543709860 |
| Schedule B: | 8543709665 |