CY7S1061GE30-10BVXI

The CY7S1061GE is a high-performance CMOS fast static RAM organized as 1,048,576 words by 16 bits. This device features fast access times (10 ns) and a unique ultra-low power Deep Sleep mode. The device also features embedded ECC. ECC logic can detect and correct single-bit error in the accessed location. The CY7S1061GE device includes an ERR pin that signals an error-detection and correction event during a read cycle.To access devices with a single-chip enable input, assert the chip enable input (CE\) LOW. To access dual chip enable devices, assert both chip enable inputs – CE1\ as LOW and CE2 as HIGH. To perform data writes, assert the Write Enable (WE\) input LOW, and provide the data and address on device data pins (I/O0 through I/O15) and address pins (A0 through A19) respectively. The Byte High Enable (BHE\) and Byte Low Enable (BLE\) inputs control byte writes, and write data on the corresponding I/O lines to the memory location specified. BHE\ controls I/O8 through I/O15 and BLE\ controls I/O0 through I/O7.To perform data reads, assert the Output Enable (OE\) input and provide the required address on the address lines. Read data is accessible on the I/O lines (I/O0 through I/O15). You can perform byte accesses by asserting the required byte enable signal (BHE\ or BLE\) to read either the upper byte or the lower byte of data from the specified address location.All I/Os (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE\ HIGH for single chip enable devices and CE1\ HIGH and CE2 LOW for dual chip enable devices), or the control signals (OE\, BLE\, BHE\) are de-asserted. The device is placed in a low power Deep Sleep mode when the Deep Sleep pin (DS\) is LOW. In this state, the device is disabled for normal operation and is placed in a data retention mode. The device can be activated by de-asserting the Deep Sleep pin (DS\ HIGH).The CY7S1061GE is available in 48-pin TSOP I, 54-pin TSOP II, and 48-ball VFBGA packages.

• High speed
  • tAA = 10 ns
• Ultra-low power PowerSnooze™device
  • Deep Sleep (DS) current Ids = 22-µA maximum
• Low active and standby currents
  • Icc = 90-mA typical
  • Isb2 = 20-mA typical
• Wide operating voltage range: 2.2 V to 3.6 V
• Embedded error-correcting code (ECC) for single-bit error correction
• 1.0-V data retention
• Transistor-transistor logic (TTL) compatible inputs and outputs
• Error indication (ERR) pin to indicate 1-bit error detection and correction
• Available in Pb-free 48-pin TSOP I, 54-pin TSOP II, and 48-ball VFBGA packages