CY7S1041GE30-10BVXI

The CY7S1041GE30 is a high-performance PowerSnooze static RAM organized as 256K words × 16 bits. This device features fast access times (10 ns) and a unique ultra-low power Deep-Sleep mode. With Deep-Sleep mode currents as low as 15 µA, the CY7S1041GE30 devices combine the best features of fast and low- power SRAMs in industry-standard package options. The device also features embedded ECC. logic which can detect and correct single-bit errors in the accessed location. Deep-Sleep input (DS\) must be deasserted HIGH for normal operating mode.To perform data writes, assert the Chip Enable (CE\) and Write Enable (WE\) inputs LOW, and provide the data and address on device data pins (I/O0 through I/O15) and address pins (A0 through A17) respectively. The Byte High Enable (BHE\) and Byte Low Enable (BLE\) inputs control byte writes, and write data on the corresponding I/O lines to the memory location specified. BHE controls I/O8 through I/O15 and BLE\ controls I/O0 through I/O7.To perform data reads, assert the Chip Enable (CE\) and Output Enable (OE\) inputs LOW and provide the required address on the address lines. Read data is accessible on the I/O lines (I/O0 through I/O15). You can perform byte accesses by asserting the required byte enable signal (BHE\ or BLE\) to read either the upper byte or the lower byte of data from the specified address location.The device is placed in a low-power Deep-Sleep mode when the Deep-Sleep input (DS) is asserted LOW. In this state, the device is disabled for normal operation and is placed in a low power data retention mode. The device can be activated by deasserting the Deep-Sleep input (DS) to HIGH. The CY7S1041G is available in 48-ball VFBGA and 44-pin (400-mil) Molded SOJ.

• High speed
  • Access time (tAA) = 10 ns / 15 ns
• Ultra-low power Deep-Sleep (DS) current
  • Ids = 15 µA
• Low active and standby currents
  • Active Current Icc = 38-mA typical
  • Standby Current Isb2 = 6-mA typical
• Wide operating voltage range: 2.2 V to 3.6 V
• Embedded ECC for single-bit error correction
• 1.0-V data retention
• TTL- compatible inputs and outputs
• Error indication (ERR) pin to indicate 1-bit error detection and correction
• Available in Pb-free 44-pin TSOP II and 48-ball VFBGA