CY7C2665KV18-550BZXI

The CY7C2665KV18 is 1.8 V synchronous pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus that exists with common I/O devices. Each port is accessed through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock. Accesses to the QDR II+ read and write ports are completely independent of one another. To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with four 18-bit words (CY7C2663KV18), or 36-bit words (CY7C2665KV18) that burst sequentially into or out of the device. Because data is transferred into and out of the device on every rising edge of both input clocks (K and K), memory bandwidth is maximized while simplifying system design by eliminating bus “turn arounds”.

• Separate independent read and write data ports
  • Supports concurrent transactions
• 550-MHz clock for high bandwidth
• Four-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MHz
• Available in 2.5-clock cycle latency
• Two input clocks (K and K) for precise DDR timing
  • Static random access memory (SRAM) uses rising edges only
• Echo clocks (CQ and CQ) simplify data capture in high-speed systems
• Data valid pin (QVLD) to indicate valid data on the output
• On-die termination (ODT) feature
  • Supported for D[x:0], BWS[x:0], and K/K inputs
• Single multiplexed address input bus latches address inputs for read and write ports
• Separate port selects for depth expansion
• Synchronous internally self-timed writes
• Quad data rate (QDR®) II+ operates with 2.5-cycle re