CY7C25442KV18-333BZI

The CY7C25442KV18 is 1.8-V synchronous pipelined SRAMs, equipped with QDR II+ architecture. Similar to the QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to “turn around” the data bus that exists with common devices. Access to each port is through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock. Accesses to the QDR II+ read and write ports are independent of one another. To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with two 36-bit words (CY7C25442KV18) that burst sequentially into or out of the device. Because data can be transferred into and out of the device on every rising edge of both input clocks (K and K), memory bandwidth is maximized while simplifying system design by eliminating bus “turnarounds”. These devices have an on-die termination feature supported for D[x:0], BWS[x:0], and K/K inputs, which helps eliminate external termination resistors, reduce cost, reduce board area, and simplify board routing. Depth expansion is accomplished with port selects, which enables each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

• Separate independent read and write data ports
  • Supports concurrent transactions
• 333-MHz clock for high bandwidth
• Two-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz
• Available in 2.0 clock cycle latency
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Echo clocks (CQ and CQ) simplify data capture in high speed systems
• Data valid pin (QVLD) to indicate valid data on the output
• On-die termination (ODT) feature
  • Supported for D[x:0], BWS[x:0], and K/K inputs
• Single multiplexed address input bus latches address inputs for both read and write ports
• Separate port selects for depth expansion
• Synchronous internally self-timed writes
• QDR® II+ operates with 2.0 cycle read latency when DOFF is asserted HIGH