CY7C1648KV18-400BZXC

The CY7C1648KV18 are 1.8-V synchronous pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K/. Read data is driven on the rising edges of K and K/. Each address location is associated with two18-bit words (CY7C1648KV18) that burst sequentially into or out of the device.Asynchronous inputs include an output impedance matching input (ZQ). Synchronous data outputs (Q, sharing the same physical pins as the data inputs D) are tightly matched to the two output echo clocks CQ/CQ/, eliminating the need for separately capturing data from each individual DDR SRAM in the system design.All synchronous inputs pass through input registers controlled by the K or K/ input clocks. All data outputs pass through output registers controlled by the K or K/ input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

• 144-Mbit density (8 M × 18, 4 M × 36)
• 450-MHz clock for high bandwidth
• Two-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces (data transferred at 900 MHz) at 450 MHz
• Available in 2.0-clock cycle latency
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Echo clocks (CQ and CQ/) simplify data capture in high-speed systems
• Data valid pin (QVLD) to indicate valid data on the output
• Synchronous internally self-timed writes
• DDR II+ operates with 2.0-cycle read latency when DOFF/ is asserted high
• Operates similar to DDR I device with one cycle read latency when DOFF/ is asserted low
• Core Vdd = 1.8 V ± 0.1 V; I/O Vddq = 1.4 V to Vdd
  • Supports both 1.5 V and 1.8 V I/O supply
• High-speed transceiver logic (HSTL) inputs and variable drive HSTL output buffers
• Available in 165-ball fine-pitch ball