CY7C1612KV18-300BZXI

The CY7C1612KV18 is 1.8-V synchronous pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II architecture has separate data inputs and data outputs to completely eliminate the need to ‘turn around’ the data bus that exists with common I/O devices. Access to each port is through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock. Accesses to the QDR II read and write ports are completely independent of one another. To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with two 18-bit words (CY7C1612KV18) that burst sequentially into or out of the device. Because data can be transferred into and out of the device on every rising edge of both input clocks (K and K and C and C), memory bandwidth is maximized while simplifying system design by eliminating bus turnarounds. Depth expansion is accomplished with port selects, which enables each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

• Separate independent read and write data ports
  • Supports concurrent transactions
• 333-MHz clock for high bandwidth
• Two-word burst on all accesses
• Double data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
• Echo clocks (CQ and CQ) simplify data capture in high-speed systems
• Single multiplexed address input bus latches address inputs for both read and write ports
• Separate port selects for depth expansion
• Synchronous internally self-timed writes
• Quad data rate (QDR®) II operates with 1.5-cycle read latency when DOFF is asserted high
• Operates similar to QDR I device with 1 cycle read latency when DOFF is asserted low
• Available in × 9, × 18,