CY7C1470V33-167AXC

The CY7C1470V33 is a 3.3 V, 2 M × 36/4 M × 18/1 M × 72 synchronous pipelined burst SRAMs with No Bus Latency (NoBL logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1470V33 is equipped with the advanced (NoBL) logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent write/read transitions. The CY7C1470V33 is pin compatible and functionally equivalent to ZBT devices.

• Pin compatible and functionally equivalent to ZBT
• Supports 200 MHz Bus operations with zero wait states
  • Available speed grades are 200 and 167 MHz
• Internally self timed output buffer control to eliminate the need to use asynchronous
• Fully registered (inputs and outputs) for pipelined operation
• Byte write capability
• Single 3.3 V power supply
• 3.3 V/2.5 V I/O power supply
• Fast clock-to-output time
  • 3.0 ns (for 200 MHz device)
• Clock enable (CE/ and OE/?) pin to suspend operation
• Synchronous self timed writes
• CY7C1470V33 available in JEDEC-standard Pb-free 100-pin TQFP
• IEEE 1149.1 JTAG boundary scan compatible
• Burst capability - linear or interleaved burst order
• “ZZ” sleep mode option and stop clock option