CY7C1470V25-200BZI

CY7C1470V25-200BZI is a CY7C1470V25 synchronous pipelined burst SRAM with No Bus Latency™. This is designed to support unlimited true back-to-back read/write operations with no wait states. It is equipped with the advanced (NoBL) logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent write/read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Three synchronous chip enables active-low (CE1, CE2, CE3) and an asynchronous output enable active-low (OE) provide for easy bank selection and output tri-state control. In order to avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence.

• Pin-compatible and functionally equivalent to ZBT™
• Supports 200MHz bus operations with zero wait states
• Internally self-timed output buffer control to eliminate the need to use asynchronous active-low OE
• Fully registered (inputs and outputs) for pipelined operation
• Byte write capability, single 2.5V power supply
• 2.5V I/O supply (VDDQ), fast clock-to-output times
• Synchronous self-timed writes, IEEE 1149.1 JTAG boundary scan compatible
• 165-ball FBGA package
• Industrial temperature rating range from –40°C to +85°C