CY7C1380KV33-250AXC

The CY7C1380KV33 SRAM integrates 524,288 × 36 and 1,048,576 × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable, depth-expansion chip enables, burst control inputs , write enables , and global write . Asynchronous inputs include the output enable and the ZZ pin.

Addresses and chip enables are registered at rising edge of clock when address strobe processor or address strobe controller are active. Subsequent burst addresses can be internally generated as they are controlled by the advance pin.

• Supports bus operation up to 250 MHz
• Available speed grades are 250, 200, and 167 MHz
• Registered inputs and outputs for pipelined operation
• 3.3 V core power supply
• 2.5V or 3.3 V I/O power supply
• Fast clock-to-output times
  • 2.5 ns (for 250 MHz device)
• Provides high performance 3-1-1-1 access rate
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Single cycle chip deselect
• Available in JEDEC-standard Pb-free 100-pin TQFP and non Pb-free 165-ball FBGA package
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• ZZ sleep mode option