CY7C1338G-100AXC

The CY7C1338G is a 128 K × 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 8.0 ns (100-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK).

• 128 K × 32 common I/O
• 3.3 V core power supply (VDD)
• 2.5 V or 3.3 V I/O supply (VDDQ)
• Fast clock-to-output times
  • 8.0 ns (100-MHz version)
• Provide high-performance 2-1-1-1 access rate
• User-selectable burst counter supporting Intel? Pentium? interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Offered in Pb-free 100-pin TQFP package
• “ZZ” sleep mode option