CY7C1061G30-10ZSXIT
SRAM Chip Async Single 3V 16M-Bit 1M x 16 10ns 54-Pin TSOP-II T/R
CY7C1061G30-10ZSXIT is a CY7C1061G 16Mbit (1M words × 16bit) static RAM with error-correcting code (ECC). To access device with a single chip enable input, assert the chip enable active-low (CE) input LOW. To access dual chip enable devices, assert both chip enable inputs active-low CE1 as LOW and CE2 as HIGH. All I/Os (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected active-low (CE HIGH for a single chip enable device and active-low CE1 HIGH / CE2 LOW for a dual chip enable device), or control signals are de-asserted active-low (OE, BLE, BHE).
- Embedded error-correcting code (ECC) for single-bit error correction
- Low active and standby currents are ICC = 90mA typical at 100MHz, ISB2 = 20mA typical
- 1.0V data retention
- Transistor-transistor logic (TTL) compatible inputs and outputs
- Error indication (ERR) pin to indicate 1-bit error detection and correction
- 10ns speed, 2.2V–3.6V voltage range
- 54-pin TSOP II package
- Dual chip enable
- Industrial ambient temperature range from –40°C to +85°C
- 110mA maximum operating current ICC
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| 20 Bit | ||
| 16 Mbit | ||
| TSOP-II | ||
| Surface Mount | ||
| Pure Tin | ||
| 260 | ||
| 110 mA | ||
| 10 ns | ||
| 1M x 16bit | ||
| 16 Mbit | ||
| Surface Mount | ||
| MSL 3 - 168 hours | ||
| 54 | ||
| 16 Bit | ||
| 16 Bit | ||
| 1 | ||
| 1 MWords | ||
| -40 to 85 °C | ||
| 85 °C | ||
| -40 °C | ||
| 54TSOP-II | ||
| 54 | ||
| 22.517(Max) x 10.262(Max) x 1.05(Max) | ||
| No | ||
| Industrial | ||
| Asynchronous SRAM | ||
| TSOP-II | ||
| 3.6 V | ||
| 2.2 V | ||
| 3 V | ||
| 3.0000 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | RECOVERY FEE |
| ECCN: | 3A991.B.2.B |
| HTSN: | 8542320041 |
| Schedule B: | 8542320040 |
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