CY7C1061DV33-10ZSXI

The CY7C1061DV33 is a high performance CMOS Static RAM organized as 1,048,576 words by 16 bits. To write to the device, take Chip Enables and Write Enable input LOW. If Byte Low Enable is LOW, then data from I/O pins, is written into the location specified on the address pins. If Byte High Enable is LOW, then data from I/O pins is written into the location specified on the address pins. To read from the device, take Chip Enables and Output Enable LOW while forcing the Write Enable HIGH. If Byte Low Enable is LOW, then data from the memory location specified by the address pins appears on I/O0 to I/O7. If Byte High Enable is LOW, then data from memory appears on I/O8 to I/O15. The input or output pins are placed in a high impedance state when the device is deselected the outputs are disabled, the BHE and BLE are disabled, or during a write operation. The CY7C1061DV33 is available in a 54-pin TSOP II package with center power and ground (revolutionary) pinout, and 48-ball VFBGA packages.

• High speed
  • tAA = 10 ns
• Low active power
  • ICC = 175 mA at 100 MHz
• Low CMOS standby power
  • ISB2 = 25 mA
• Operating voltages of 3.3 ± 0.3 V
• 2.0 V data retention
• Automatic power down when deselected
• TTL compatible inputs and outputs
• Easy memory expansion with CE1 and CE2 features
• Available in Pb-free 54-pin TSOP II and 48-ball VFBGA packages
• Offered in single CE and dual CE options