CY7C10612GE30-10ZSXIT

The CY7C10612GE are high performance CMOS fast static RAM devices with embedded ECC. both device are offered in single chip enable option. The CY7C10612GE device includes an error indication pin that signals an error-detection and correction event during a read cycle. To write to the device, take Chip Enables (CE\) and Write Enable (WE\) input LOW. If Byte Low Enable (BLE\) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A19). If Byte High Enable (BHE\) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19). To read from the device, take Chip Enable (CE\) and Output Enable (OE\) LOW while forcing the Write Enable (WE\) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on I/O0 to I/O7. If Byte High Enable (BHE) is LOW.The input or output pins (I/O0 through I/O15) are placed in a high impedance state when the device is deselected (CE\ HIGH), the outputs are disabled (OE\ HIGH), the BHE\ and BLE\ are disabled (BHE\, BLE\ HIGH), or during a write operation (CE\ LOW and WE\ LOW). On the CY7C10612GE devices the detection and correction of a single-bit error in the accessed location is indicated by the assertion of the ERR output (ERR = high). The CY7C10612GE are available in a 54-pin TSOP II package.

• High speed: tAA = 10 ns
• Embedded error-correcting code (ECC) for single-bit errorcorrection
• Low active power
  • Icc = 90 mA typical
• Low CMOS standby power
  • Isb2 = 20 mA typical
• Operating voltages of 3.3 ± 0.3 V
• 1.0 V data retention
• Transistor-transistor logic (TTL) compatible inputs and outputs
• ERR pin to indicate 1-bit error detection and correction
• Available in Pb-free 54-pin TSOP II package