CY7C1011DV33-10ZSXIT
SRAM Chip Async Single 3.3V 2M-Bit 128K x 16 10ns 44-Pin TSOP-II T/R
The CY7C1011DV33 is a high-performance CMOS Static RAM organized as 128 K words by 16 bits. Writing to the device is accomplished by taking Chip Enable and Write Enable inputs LOW. If Byte Low Enable is LOW, then data from I/O pins, is written into the location specified on the address pins. If Byte High Enable (BHE) is LOW, then data from I/O pins is written into the location specified on the address pins.
- Pin and function compatible with CY7C1010CV33
- High speed
- tAA = 10 ns
- Low active power
- ICC = 90 mA at 10 ns
- Low CMOS standby power
- ISB2 = 10 mA
- 2.0 V data retention
- Automatic power down when deselected
- TTL-compatible inputs and outputs
- Easy memory expansion with CE/ and OE/ and features
- Available in Pb-free 36-pin SOJ and 44-pin TSOP II packages
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| 17 Bit | ||
| 2 Mbit | ||
| TSOP-II | ||
| Surface Mount | ||
| Gold|Matte Tin | ||
| 260 | ||
| 90 mA | ||
| 10 ns | ||
| 128K x 16bit | ||
| 2 Mbit | ||
| Surface Mount | ||
| MSL 3 - 168 hours | ||
| 44 | ||
| 16 Bit | ||
| 16 Bit | ||
| 1 | ||
| 128 kWords | ||
| -40 to 85 °C | ||
| 85 °C | ||
| -40 °C | ||
| 44TSOP-II | ||
| 44 | ||
| 18.52 x 10.26 x 1.04 mm | ||
| No | ||
| Industrial | ||
| Asynchronous SRAM | ||
| TSOP-II | ||
| 3.6 V | ||
| 3 V | ||
| 3.3 V | ||
| Asynchronous | ||
| 3.3000 V |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | NO RECOVERY FEE |
| ECCN: | 3A991.B.2.B |
| HTSN: | 8542320041 |
| Schedule B: | 8542320040 |
Factory Lead Time: