CY7C09279V-7AXC

The CY7C09279V are high speed 3.3 V synchronous CMOS 16 K, 32 K, and 64 K × 16 and 16 K and 64 K × 18 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory [11]. Registers on control, address, and data lines allow for minimal setup and hold times. In pipelined output mode, data is registered for decreased cycle time and clock to data valid tCD2 = 7.5 ns [12] (pipelined). Flow through mode can also be used to bypass the pipelined output register to eliminate access latency. In flow through mode, data is available tCD1 = 18 ns after the address is clocked into the device. Pipelined output or flow through mode is selected through the FT/Pipe pin. Each port contains a burst counter on the input address register. The internal write pulse width is independent of the LOW to HIGH transition of the clock signal. The internal write pulse is self timed to allow the shortest possible cycle times.

• True dual-ported memory cells that allow simultaneous access of the same memory location
• Six flow through/pipelined devices:
  • 16 K × 16 / 18 organization (CY7C09269V/369V)
  • 32 K × 16 organization (CY7C09279V)
  • 64 K × 16 / 18 organization (CY7C09289V/389V)
• Three modes:
  • Flow through
  • Pipelined
  • Burst
• Pipelined output mode on both ports allows fast 100 MHz operation
• 0.35 micron CMOS for optimum speed and power
• High speed clock to data access: 7.5[1], 9, 12 ns (max)
• 3.3 V low operating power:
  • Active = 115 mA (typical)
  • Standby = 10 ?A (typical)
• Fully synchronous interface for easier operation
• Burst counters increment addresses internally:
  • Shorten cycle times
  • Minimize bus noise
  • Supported in flow through and pipelined modes
• Dual chip enables easy depth expansion
• Upper and lower byte