CY7C024E-25AXI

The CY7C024E is low-power CMOS 4K × 16 and 8K × 16/18 dual-port static RAMs. Various arbitration schemes are included on the CY7C024E and CY7C025E/CY7C0251E to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The CY7C024E and CY7C025E/CY7C0251E can be used as standalone 16 or 18-bit dual-port static RAMs or multiple devices can be combined to function as a 32-/36-bit or wider master/ slave dual-port static RAM. An M/? pin is provided for implementing 32-/36-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory.

• True dual-ported memory cells that allow simultaneous reads of the same memory location
• 4 K × 16 organization (CY7C024E)
• 0.35-µ complementary metal oxide semiconductor (CMOS) for optimum speed and power
• High-speed access: 15 ns
• Low operating power: ICC = 180 mA (typ), ISB3 = 0.05 mA (typ)
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 32/36 bits or more using master/slave chip select when using more than one device
• On-chip arbitration logic
• Semaphores included to permit software handshaking between ports
• INT/ flag for port-to-port communication
• Separate upper-byte and lower-byte control
• Pin select for master or slave
• Available in Pb-free 100-pin thin quad flatpack (TQFP) package