CY7B9945V-2AXC
Clock Buffer, 24 MHz to 200 MHz, 11 Outputs, 2.97 V to 3.63 V, 52 Pins, TQFP
- RoHS 10 Compliant
- Tariff Charges
The CY7B9945V high speed multi-phase PLL clock buffer offers user selectable control over system clock functions. This multiple output clock driver provides the system integrator with functions necessary to optimize the timing of high performance computer and communication systems. The device features a guaranteed maximum TTB window specifying all occurrences of output clocks. This includes the input reference clock across variations in output frequency, supply voltage, operating temperature, input edge rate, and process. Ten configurable outputs each drive terminated transmission lines with impedances as low as 50W while delivering minimal and specified output skews at LVTTL levels. The outputs are arranged in two banks of four and six outputs. These banks enable a divide function of 1 to 12, with phase adjustments in 625 ps–1300 ps increments up to ±10.4 ns. The dedicated feedback output enables divide-by functionality from 1 to 12 and limited phase adjustments. However, if needed, any one of the ten outputs can be connected to the feedback input as well as driving other inputs. Selectable reference input is a fault tolerant feature that enables smooth change over to a secondary clock source when the primary clock source is not in operation. The reference inputs and feedback inputs are configurable to accommodate both LVTTL or Differential (LVPECL) inputs. The completely integrated PLL reduces jitter and simplifies board layout.
- 500 ps max Total Timing Budget (TTB™) window
- 24 MHz-200 MHz input and Output Operation
- Low Output-output skew <200 ps
- 10 + 1 LVTTL outputs driving 50 ? terminated lines
- Dedicated feedback output
- Phase adjustments in 625 ps/1300 ps steps up to +10.4 ns
- 3.3 V LVTTL/LVPECL, Fault Tolerant, and Hot Insertable Reference Inputs
- Multiply or Divide Ratios of 1 through 6, 8, 10, and 12
- Individual Output Bank Disable
- Output High Impedance Option for Testing Purposes
- Integrated Phase Locked Loop (PLL) with Lock Indicator
- Low Cycle-cycle jitter (<100 ps peak-peak)
- 3.3 V Operation
- Industrial Temperature Range: -40 °C to +85 °C
- 52-pin 1.4 mm TQFP package
Technical Attributes
Find Similar Parts
| Description | Value | |
|---|---|---|
| Clock Buffer | ||
| 200 MHz | ||
| 24 MHz | ||
| LVPECL, LVTTL | ||
| 2 | ||
| 11 | ||
| 52 | ||
| 70 °C | ||
| 0 °C | ||
| LVTTL | ||
| CY7B9945V Series | ||
| 3.63 Vdc | ||
| 2.97 Vdc |
ECCN / UNSPSC / COO
| Description | Value |
|---|---|
| Country of Origin: | PROJECTED FEE |
| ECCN: | EAR99 |
| HTSN: | 8542390090 |
| Schedule B: | 8542390060 |